1. Field
The invention relates generally to computer systems, and in particular, to computer systems that employ a method for dual memory channel interleaving.
2. Background Information
For bandwidth intensive operations like graphics and MPEG, two channels of memory may be required to provide sufficient data bandwidth. In a dual memory channel system, the two channels can be accessed in two different ways. The first approach is to treat them as completely independent memory ports, where any memory access goes to one channel and the two channels are accessed completely independently of each other. The second approach is to interleave the two channels, so that any memory access is sent to both the channels, and both channels operate in lock-step of each other.
When dealing with memory operands (e.g. graphic surfaces) that are inherently rectangular in nature, certain functions within the graphics device support the storage/access of the operands using tiled memory formats in order to increase performance. Rectangular memory operands have a specific width and height, and are considered as residing within an enclosing rectangular region whose width is considered the pitch of the region and surfaces contained within. Surfaces stored within an enclosing region must have widths less than or equal to the region pitch.
The simplest storage format is the linear format, where each row of the operand is stored in sequentially increasing memory locations. If the surface width is less than the enclosing region's pitch, there will be additional memory storage between rows to accommodate the region's pitch. The pitch of the enclosing region determines the distance (in the memory address space) between vertically adjacent operand elements.
The linear format is best suited for one-dimensional row-sequential access patterns (e.g., a display surface where each scan line is read sequentially). Here the fact that one object element may reside in a different memory page than its vertically adjacent neighbors is not significant. All that matters is that horizontally adjacent elements are stored contiguously. However, when a device function needs to access a 2D sub-region within an operand (e.g., a read or write of a 4×4 pixel span), having vertically adjacent elements fall within different memory pages is to be avoided, as the page crossings required to complete the access typically incur increased memory latencies (and therefore lower performance).
One solution to the problem is to divide the enclosing region into an array of smaller rectangular regions, called memory tiles. Surface elements falling within a given tile will all be stored in the same physical memory page, thus eliminating page-crossing penalties for 2D sub-region accesses within a tile and thereby increasing performance. The rearrangement of the surface elements in memory must be accounted for in functions operating upon tiled surfaces. This requires either the modification of an element's linear memory address or an alternate formula to convert an element's X, Y coordinates into a tiled memory address. However, before tiled address generation can take place, some mechanism must be used to determine whether the surface elements accessed fall in a linear or tiled region of memory, and if tiled, what the tile region pitch is, and whether the tiled region uses X-major or Y-major format.
What is need therefore is a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity.